The gated SR latch is a fundamental building block in digital circuits, used to store a single bit of information. It consists of two cross-coupled NOR gates, with inputs designated as S (Set) and R (Reset), and an enable input denoted as G (Gate). However, a regular gated SR latch suffers from a critical issue: the potential for an undefined state when both S and R are set to logic '1' simultaneously. This undefined behavior can lead to unpredictable circuit operation and system malfunctions. To address this limitation, we can modify the gated SR latch to create a set-dominant gated SR latch, which ensures a predictable output even when both S and R are high.
Understanding Set-Dominant Gated SR Latch
A set-dominant gated SR latch is a variation of the traditional gated SR latch that prioritizes the "Set" input. In this configuration, the output Q will always be set to '1' when both S and R are set to '1' and the gate input (G) is enabled. Here's a breakdown of the key differences:
Traditional Gated SR Latch Behavior:
- S = 0, R = 0: The latch holds its previous state.
- S = 1, R = 0: The latch sets Q = 1 and Q' = 0.
- S = 0, R = 1: The latch resets Q = 0 and Q' = 1.
- S = 1, R = 1: The latch enters an undefined state, where both Q and Q' may be either 0 or 1.
Set-Dominant Gated SR Latch Behavior:
- S = 0, R = 0: The latch holds its previous state.
- S = 1, R = 0: The latch sets Q = 1 and Q' = 0.
- S = 0, R = 1: The latch resets Q = 0 and Q' = 1.
- S = 1, R = 1: The latch sets Q = 1 and Q' = 0 (Set dominates).
Implementing the Set-Dominant Gated SR Latch:
The key to achieving the set-dominant behavior lies in modifying the NOR gate logic associated with the output Q. Here's the implementation using NAND gates:
1. Logic Diagram:
- Two NAND gates: One for the Q output, the other for the Q' output.
- Two inverters: One for the Set (S) input, the other for the Reset (R) input.
- A single AND gate: For the Gate (G) input.
2. Circuit Operation:
- Gate Enabled (G = 1): When G is high, the AND gate output is high, allowing the NAND gates to function normally. The latch behaves according to the standard S and R input combinations.
- S = 1, R = 1: With G enabled, the NAND gate for Q output receives a logic '0' from the inverted S input, forcing the output Q to be '1', regardless of the R input. This ensures the set-dominant behavior.
3. Truth Table:
| G | S | R | Q | Q' |
|---|---|---|---|---|
| 0 | X | X | 0 | 1 |
| 1 | 0 | 0 | Q<sub>prev</sub> | Q<sub>prev</sub>' |
| 1 | 1 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 1 | 1 | 0 |
4. Key Differences from Traditional Gated SR Latch:
- Set-Dominant Output: When S and R are both high, the latch will set Q = 1, regardless of the previous state.
- No Undefined State: The set-dominant behavior eliminates the undefined state that occurs in the traditional latch.
Advantages and Applications of the Set-Dominant Gated SR Latch:
- Predictable Output: The set-dominant gated SR latch offers a predictable output even when both S and R are high, eliminating the potential for unintended behavior.
- Reliable Storage: It provides a reliable method for storing a single bit of information.
- Versatile Applications: Used in various digital circuits, including:
- Memory cells in static RAM (SRAM)
- Clock-driven sequential circuits
- Data flip-flops with additional control features
Building a Set-Dominant Gated SR Latch with NAND Gates:
While the example above uses NAND gates, you can also build a set-dominant SR latch using NOR gates. The key is to modify the NOR gate associated with the Q output. Here's a simplified explanation:
- NOR gate for Q output: The NOR gate should be configured with an inverted R input and the normal G and S inputs. This ensures that if R is high, the output Q will be forced to '1'.
- NOR gate for Q' output: This remains unchanged, with the standard inputs for G, S, and R.
Conclusion:
The set-dominant gated SR latch is a valuable variation of the standard gated SR latch, offering a more predictable and reliable storage element for digital circuits. By prioritizing the "Set" input, it eliminates the undefined state that can occur when both S and R are high. This enhanced behavior makes it suitable for various applications, including memory cells, clock-driven sequential circuits, and more complex flip-flop designs. Understanding the set-dominant behavior and implementation techniques of this latch is essential for building robust and reliable digital circuits.